Friday, October 21, 2011

Logic synthesis and the standard cell library...

It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, we had everything before us, we had nothing before us, we were all going direct to heaven"

—The opening paragraph of A Tale of Two Cities

These feelings arise when one takes a closer look at standard cell libraries and logic synthesis tools. while standard cells library designers believe that quality of logic synthesis is only going to improve with more and more cells being designed in to the library, logic synthesis seems to throw quite a few surprises by using these cells less and less effectively.

why do synthesis users get feedback that they need assign cells to "set_dont_use/force hide" . why so many?

The explanations offered go well beyond my logical understanding.

1. Open balanced cells only for clock
2. Hide the delay buffers in a safe,which needs opening up just before hold fixing?
3. Power management cells get used to buffers long wires (I have seen level shifters in a few scenarios).So hide them and open them only when you need to use them. Pre instantiate them and don't let synthesis map to them.
4. Numerous other similar tweaks to not use more and more cells.....

Are all these set_dont_use/hide mechanisms a consequence of using a delay model inside synthesis into whose grand scheme all these unfortunate cells dont fit in?

May be the library designers need to talk more to the synthesis guys....

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