I am not sure of any existing tools which give an accurate estimate of active state leakage.
We can evaluate leakage in the typical and worst case Leakage corners (which gives us the lower and upper bounds). The problem gets exaggerated from the lower bound if the chip gets hotter than 25C.
It is interesting to note that fabs have migrated to using HighK dielectrics in the sub 40nm processes. This could have a potential impact on Threshold voltage, which means an increased VDD. Although slight, the increase in VDD cannot be taken lightly as dynamic power scales up as a square of VDD. The increased dynamic power contributes in a direct way to increase in the temperature on chip.
This in turn would increase the amount by which the chip will now leak.
There is an acute need right now for computing thermal profile of the chip. For this, an accurate estimate of dynamic power is quite essential, which is only possible through VCD/SAIF based simulations. This information then needs to provide feedback to a leakage engine which does a region based analysis of leakage on chip based on its thermal profile.
It is quite vital to have feedback between dynamic power computation, thermal profile, leakage as they are interdependent. As the chip leaks more, its temperature is bound to increase, which would cause further leakage. Hence the problem cannot be solved over 1 iteration, but can only be tackled over a few simulations. It is also quite difficult to get hold of any characterization data from the fab, which makes the problem even hard to solve. The worst case leakage picture is a typical doomsday scenario and doesnt provide much insight into the problem. what is really required is a more realistic picture.