Shrinking feature sizes->increasing die sizes->faster clocks->interconnect density->reducing supply voltages->Overbuffering? (courtesy: Henny Penny).
well..I will trust henny penny and be his humble devotee. Will I end up with higher area and more power consuming silicon? The CAD guys will tell me that my buffer counts are realistic. Buffering under elmore delay model can be off by as much as 200% in comparison to SPICE. Buffer/inverter counts can no longer be evaluated as a percentage of total gate count.
what are metrics for buffer estimation which we can rely on in the 45 and 65nm realm?
while there's more to follow in this article..Industry veterans out there, let us know your thoughts/metrics you have used and are currently using to prove the CAD guys wrong.
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