Correlation issues in a CAD flow

There can be numerous issues relating to correlation across various steps in a typical ASIC CAD flow. These issues can cause timing/area/power convergence problems in meeting ASIC tapeouts.

1. Logic Synthesis:
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At logic synthesis step not much is known about wires in the design. Wires can be estimated using statistical models based on design size and cannot be computed.

The delay calculation engine makes use of either a pessimistic or optimistic wire model.

Only post placement, we can back-annotate a reasonably accurate SDF/spef and re-do the logic synthesis step for more restructuring to model reality.

Floorplan, which plays a significant part in timing closure is not known at Logic synthesis stage.

High fanout buffering also has to be estimated and cannot be computed and delay models (like logical effort) are meant for speed (linear delay model) and not for accuracy.

NLDM and SPDM models are really not used inside a logic synthesis system as they are complex polynomial functions are too time consuming to minimize over multiple variables on complex multi million designs.

There is also no real value using such accurate models (SPDM) for delay calculation as design is not really complete by any means.

There is no clock tree at this stage, so insertion delay and skew might have to be modelled based on design experience or these values could be derieved after a quick prototyping flow.

There are synthesis tools now in the market which try to read in floorplanning information as a part of the synthesis process and quickly estimate block placements.

But remember that this could involve a tough loop for RTL/logic designer's with already tight RTL delivery schedules. Also, these tools might not be accounting for correct timing/congestion aware placement information.

2. Post placement/Global route:
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Elmore delay is a single moment delay computation technique. The model does not acount for proper slew computation/propagation.

It also does not account for resistive shielding (i.e the gate does not see an effective capacitance but will see the total capacitance as load). This makes the model pessimistic.

This is good news towards a global to final mode closure as all this is pessimism getting added in the design flow inherently to over constrain physical optimization algorithms.

Via's are not inserted at this stage of the design flow. Rather they could be modelled. Depending on the modelling technique used, it can effect global mode via resistance calculation.

Estimating crosstalk at this stage can be very tricky as track assignment is not yet complete and coupling capacitances can only be predicted and not computed. This could be achieved by some means of virtual track assignment.

But all this is going to add additional run time to GR updates, incremental GR updates and the flow.

How many tools you know of account for crosstalk pessimism at global mode stage?

A reasonable thing to do in STA here sounds like propagating the worst AT signal + worst slew forward in the timing engine so that some more pessimism is built into the physical synthesis process.

Another valuable point to look at this stage is to monitor the design congestion. May be we could club congestion metric to the x-talk metric and derive a statistical model for x-talk at GR stage of the design flow to account for extra margins during the physical synthesis step?

3. Post final route:
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Yeah I finished 1 and 2 and goto 3. Now I do whatever optimizations perimitted at CTS (useful skew), track routing and OCV optimization stages(common path pessimism removal). But I still have a lot of difficulty closing my design by a couple of hundred pico seconds.

The problem is small restructuring still can't be performed post layout (final routing) and the final route could have potentially detoured from the original global route topology in fixing the LVS/DRC violations.

The chance of this happening is much less in less congested designs as final routes likes to follow the global routing topologies as much as possible. Also if the cad tool is trying to minimize (sigma (global wire length(i) -final wire length(i})).

Whatever optimization happens post layout is a incremental/eco kind of optimization which will effect steps like sizing, buffering, placement and routing to an incremental extent.

Eco optimization happens with most tools reverting back to an elmore delay model internally to save on computer memory and run times. Here again the slew modelling could be off if this is the case.

Sizing/Buffering using an accurate delay model is absolutely essential at this stage. So tools have to ideally make use of multipole models. But is this the case?

Most Optimiziation commands use an internal call to the extractor and delay calculator. The extractor comes up with an unreduced RC network.

The job of the delay calculator is to build a reduced RC network taking in to account only the dominant poles (and zero's). This process is called MOR (model order reduction) and a reasonably accurate technique to do this is Asymptotic waveform evaluation (AWE). AWE when computed using Pade via Lanczos or Arnoldi method is a resonably accurate delay calculation technique.

Adding margins sounds like an elegant/good solution, but margins are design dependant, could end up being pessimistic and can have a detrimental effect on chip area and power.

There are so many pessimism's/optimism's involved in the entire ASIC design process.

Let me know your thoughts on how you handled these CAD issues in your latest design projects as this infrmation could be very interesting and helpful.