In this section we discuss some of the Major Tasks involved in the design of a SOC (System On Chip).
1. Verification
2. Logic Design
3. Logic synthesis and physical optimization.
4. DFM (design for Manufacturability)/DFY (design for yield)
5. Analog/RF (Radio Frequency), Mixed signal design.
6. Testing and design for Testability.
I will describe each one in a bit more detail now...
1. Verification
Verication can be split up into--
1.1 Black Box: Not much is known about the internals of the Design
Grey Box: Few Internals exposed.
White Box: Everything internal to the design is well understood and RTL is accessible.
1.2 Assertions (ABV), Model checking (MC), Equivalence checking (EC)(sequential/combinational), Simulation, Symbolic simulation, Emulation.
1.3 Verification Languages: PSL, Sugar, SystemC, SystemVerilog, e, vera, VHDL, Verilog, c++
2. Logic design
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2.1 behavioral level : usually the specification is written at this level!
Languages: VHDL, Verilog, System Verilog, C++, systemC
2.2 Register Transfer Level : Primarily to infer hardware for ASIC and FPGA through the process of logic synthesis
2.3 Hardware/software co-design. Most Emulation technologies currently use FPGA on emulator platform and have transactor functions to communicate with software on a work station. Hence this is hardware/software codesign.
C++ and Behavioral level (Verilog/VHDL/systemVerilog/systemC) synthes tools are available in market from some of commercial CAD vendors.
Tools: Behavioral Compiler (SNPS), Catapult (MENT)
Currently to infer hardware for SOC's, logic synthesis tools are the most popular as they give a finer level of control on the logic which gets inferred. Behavioral synthesis tools just dont offer that yet!. Hence if you have to infer logic, you have to write RTL.
It will take a couple of years for behavioral synthesis to mature to a level where it can give hardware designers more degrees of freedom (area/timing/power) and finer level of control.
3. Logic synthesis and Physical design Tools :
Few examples are: Design Compiler, Physical Compiler, ICC, First Encounter, nanoRoute.. etc)
3.1 Lots of sub problems to solve in this particular domain.
3.2 Primarily split up into these major sub problems
3.2.1 Analysis/Elaboration (compiler theory).
High level optimization
FSM state encoding
sharing and Merging of operators
RTL clock gating
Module Compilers
3.2.2 Logic optimization
Primarily split into 2 level, multi-level, Multi-valued
Literal reduction [boolean and algebraic factorization]
Decomposition
Extraction
Tree height reduction (KMS, lengauer)
Technology Mapping for area/timing/power [dag covering, BDD mapper]
Logic Restructuring [for speeding up a circuit]
Making architectural tradeoffs between design ware components for speed/area
Handling Fanout/Load
Removing Hanging logic
Redundancy Removal
Collapsing logic
Loop breaking
Dont care optimization
Retiming
gate Sizing
Gain Based synthesis
3.2.3 Floorplanning/ Floorplacement (simultaneous macro + std cell placement)
Recursive Bisectioning
Analtycal Placers
Multi level Placers
Simulated Annealing (few iterations)
3.2.4 physical optimization which is
Partitioning:
Objectives: wirelength
Algorithms: KL/FM/HMetis (k-way Hypergraph partitioning)/Multilevel Methods
Placement (Global/detailed)
Objectives:wirelength, Congestion, Timing, Legalization, noise
Algorithms: Recursive Bisectioning, MLP, APlace, capo, fengShui, Timberwolf, QPlace
Wirelength prediction, buffer estimation are also included in every iteration of placement. some placers quickly calculate steiner wirelength in each iteration
Buffering
Objectives: Load, fanout, Area, Power, slew, slack, Crosstalk
Algorithms: VGBA (Van Ginneken Buffering Algorithm)
Gate Sizing
Objectives: std cell area, slew, slack, Load, leakage, Crosstalk
Algorithms::LP, GP, Convex Porgramming
Research: Transisor sizing. On the fly library characterization
Routing (Global, track and detailed)
Objectives: wirelength reduction, timing, congestion, Crosstalk, DRC
Algorithms: Maze running, Line searching, Channel Routing, Stub routing, Steiner Trees (global), BRBC heuristics, Lots of approximation algorithms, Dijkstra's algorithm, Linear Porgramming, Randomized algorithms
There are gridded as well as Gridless routers now. But fundamentally I would guess all routers work on a grid and the grid only keeps getting smaller and is limited by the manufacturing grid.
3.3 Power distribution
Objective: to supply power to all logic elements with minimum IR drop
Minimize congestion because of metal utilization
Reduce transients during switching of power (Decap Insertion).
Automated power grid synthesis tools are getting stronger day by day. These tools are making use of Algebraic Multi-grid methods, which previously were used for solving elliptic partial differential equations.
3.4 power/rail/em analysis and power grid design
Objective: to check reliability of power grid
Tools: Incremental rail analysis /optimization is an active area of research. Matrix solvers are used to solve KCL/KVL. Conjugate gradient method is quite a popular candidate here for solving sparse linear matrices.
3.5 Clock Tree synthesis
Objectives:: Minimize Insertion delay/Minimize skew/Minimize power in distributing clocks to sequential elements
Algorithms:: MME (Method of means and medians), DME (Deferred Merge embedding)
3.6 leakage/dynamic power optimization
Objectives:: To save battery power.
Techniques: Multi Vt swapping (LP Formulation), Multi-Vdd (voltage islands), sleep modes, reduce switching probabilities in logic re-structuring
3.6 LVS/DRC
Objectives:: To check manufacturability of the chip
Mostly geometric algorithms for fast polygon manipulation for detecting DRC's. Fixing is done by router adhering to routing rules.
3.7 RLC Extraction
Objectives:: Accuracy of extraction is important as this information is passed to delay calculation engine
Targets for algorithms:: Accuracy of model, memory, run time
Types of extractors: 2.5D and 3D
3D extraction uses Maxwell's equations/Greens function to model RLC of small geometries and for rule generation purposes for 2.5D extractor. This is most accurate form of extraction (QuickCap/Raphael)
2.5D extractor uses the rules generated by 3D extractor with interpolation/Extrapolation (starRCXT)
Algorithms:: Model Order Reduction techniques for reducing size of RC networks so that they become managable. (PRIMA/PRIMO). Lots of new MOR techniques coming up every day. AWE is the most popular in the digital logic. refer to Larry Pillegi's link in the Link's section.. :)
3.8 Timing (Static timing analysis/statistical static timing analysis!)
Statistical timing is gaining popularity
Objective: Accuracy in timing without Multi-corner analysis
Algorithms: use process spread information in calculating timing spread
predict yield
Path based and block based approaches
Tool: PTSI
3.9 Noise avoidance and Repair
Exraction of coupling cap fed to delay calculator to find out crosstalk delta
Fixing done using track spacing and non default rules
Sizing of gates/buffers to reduce Agressor slew
Timing window methods to reduce crosstalk delta pessimism
3.10 OCV analysis and Optimization
Objective:: To account for process spread within and across wafers
Might be nullified with wide adoption of SSTA
Algorithms are for common path pessimism removal
4. DFM/DFY
4.1 Litho simulation Objective: How litho aware is your GDS?.
4.2 CMP checks.. Objective: Will make ECMP (electro chemical mechanical polishing) a robust process during manufacturing by checking metal density on layout.
4.3 Std cell library : tweaks to std cell libraries to increase yield
4.4 leakage power: leakage power has an impact on yield as well
Tools: Refer to Blaze DFM's wonderful site
Pondering further on point:4
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As process technology shrink from 90nm to 65nm and below (45 nm), it's difficult to manufacture such small geometries and still get a high yield (no of working chips/wafer). So manufacturability is getting tightly integrated with 3, which we discussed above. One reason which immediatly comes to mind is Lithography. While process is 45 nm, the wavelength of light used in lithography is still 153 nm (argon-fluoride and F2 laser wavelengths). Effects like diffraction are prominent. This means Litho should be taken care of in design so that these effects dont translate to silicon (done using rules for router in physical design, but this might not be the only technique). we will discuss more on each as we keep posting
5. Analog (A/D, D/A, bandgap, current mirrors, diff amps, PLL's, DLL's)
5.1 Spice
Objective: Circuit level simulator
Tools: HSPICE, PSPICE, ELDO
5.2 Analog synthesis (An active research area)
5.3 RFIC
5.4 Analog layout/Extraction
5.5 Characterization and design of std cell libraries
5.5.1 Create .lib (liberty) timing/leakage/Noise models for std cell libraries
5.6 Memory modeling and characterization
6. Test and design for Testability.
Major areas: SCAN/BIST/Test Compression/Fault Modeling/ATPG/Testers
Tester Manufacturer: Teradyne
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