on routing (Routing-2)..

Within the physical design flow of a multi million gate ASIC, one of the most critical and notoriously difficult steps to perform is Routing.

To tackle this problem, it has been split up into sub problems such as

1. Global routing
2. Track routing
3. Detail routing.

One of the most critical and initial steps is global routing. The quality of this routing solution has a direct impact on

1. chip frequency
2. Area
3. power consumption
4. cycles required to complete design cycle.

Global routing takes us to a stage where signal nets are coarsely routed under a given placement solution so that wire/via spaces are allocated to each signal net.

while the objectives at this stage are routing multi terminal nets (nets with > 2 terminals), taking net criticality/slack into account, accounting for congestion, even the most simple version of the problem (i.e routing a 2 terminal net under congestion constraints) is NP complete.

Given the advances happening in VLSI fabrication technology (<65 nm), the latest advances have posed a latest set of issues to be solved and have put further pressure on global routing technology (especially handling the Non default rules at global routing stage).