CAD and VLSI

Is this what CAD and VLSI have become?

Saturday, August 4, 2007

Dreaming in code (This was an awesome interview by Peggy Aycinena)

Read the full article at:
http://www.aycinena.com/index2/template.html?index3/archive/dreaming%20in%20code
Posted by Nick at 9:45 AM

0 comments:

Post a Comment

Newer Post Older Post Home
Subscribe to: Post Comments (Atom)

Hello. Welcome to Nick's Blog.

Here u will find my views on System On Chip Design and VLSI CAD. Please do leave your comments. I am sure we will find something interesting to talk about....

About Me

Nick
I am an ASIC designer by profession. I have been involved in all aspects of system on chip design and VLSI CAD for about 10 years now. This blog is my take on SOC/EDA technology, a window to connect with other wonderful engineers and to make friends.
View my complete profile

Subscribe To

Posts
    Atom
Posts
Comments
    Atom
Comments

Search This Blog

Loading...

Recent Books

Recent Books
Nice Book on MOS Modeling

Interesting Links

  • Asia-Pac DAC
  • Asymptotic waveform Evaluation
  • Binary Decision Diagrams
  • Blaze DFM
  • Calypto
  • Cool Verification
  • Design and Reuse
  • Design Automation Conference
  • digit life
  • Edsger.W. Dijkstra
  • Edwin. H. Armstrong
  • Insite DSP
  • International Test Conference
  • jan Melnik
  • John Busco's Home Page
  • John Ford's wonderful DFT site
  • John McGehee
  • Life without wires
  • Linux Devices
  • Martin Sauter's blog
  • Model Checking
  • Olivier's Blog

Blog Archive

  • ►  2006 (1)
    • ►  December (1)
      • vlsi cad
  • ▼  2007 (17)
    • ►  February (2)
      • Breaking down the vlsi problem into sub problems
      • 6. TESTING/ DESIGN FOR TEST
    • ►  March (7)
      • 6.1. DFT (Continued)
      • 1. VERIFICATION
      • 1.1. Formal Verification
      • 1.1.1. The Art of Equivalence Checking
      • 1.1.2 Let's blame logic synthesis
      • International work shop on Logic Synthesis
      • EDA is dead (EE-Times) ?
    • ►  April (2)
      • Dr. Stok calls for Prescriptive CAD
      • Electrons caught in the act of tunneling..
    • ►  May (3)
      • The great STA/Formal verification vs Gate level si...
      • An interesting article on cell model creation for ...
      • Gridded and gridless routers (Routing-0)
    • ►  July (1)
      • Other worries which will limit-> towards gridlessn...
    • ▼  August (1)
      • Dreaming in code (This was an awesome interview by...
    • ►  December (1)
      • courtesy:www.phdcomics.com :)
  • ►  2008 (5)
    • ►  January (2)
      • on routing (Routing-2)..
      • Design of a 50M gate ASIC..
    • ►  February (3)
      • Correlation issues in a CAD flow
      • The future of multicore.
      • It's Raining Buffers!!
  • ►  2009 (3)
    • ►  April (1)
      • High performance ARM cores and CAD Reference metho...
    • ►  October (2)
      • Does global mode hold fixing make sense?
      • ARM Osprey @ 2 GHz
Powered By Blogger