Interconnect optimization (routing) is crucial in minimizing delay, noise and optimizing reliability. Variable rules for deep submicron (width and spacing) make the job of a VLSI Router so much more difficult.
It's about how effectively we use the available space for routing with such complex design rules for < 65nm technology nodes.
Gridless routers are run time and memory intensive [when working on manufacturing grid (smallest geometry manufacturable by a fab!)]. Bringing down the run time/memory requirements is a challenge which the industry faces. This has resulted in the evolution of data structures like connection graphs and tile graphs.
Searching for paths on a uniform grid graph is so much more easier (Gridded router), but this wastes space available for routing with variable rules and new 45nm rules (litho + cmp rules!).
This is a huge topic for discussion. So Please feel free to leave behind your comments on what you think about this technology.
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