The great STA/Formal verification vs Gate level simulation debate

why the heck do we still do gate level simulations? Are they not run time/memory intensive? what is the confidence with which we can tapeout a chip without a gate level sim?

here are some views on this topic from different industry veterans at deep chip.

I didn't want to miss this interesting debate. Hence included it in the blog.

This post is from John Cooley's deepchip.com
http://www.deepchip.com/items/0421-01.html