6.1. DFT (Continued)

I wish to thank john (www.dftdigest.com) for his comments on my last post on DFT. BIST drives the scan chains in the design.

One major advantage of BIST is that the chip can test itself and hence we can reduce or avoid time on the tester all together. Testers are costly equipment and time on the tester is expensive. Tester memory/speed determine the cost of the tester and it can run into millions of dollars. So by providing some test access points for covering those faults which were tough to cover by BIST, more fault coverage can be achieved using an external tester, but with less tester time as BIST was used to get a big chunk of the coverage already!.

MBIST is widely used in the industry (almost most memories on chip have an MBIST/MBIST interface!) but logic BIST hasn't really captured the imagination of designers yet!. Logic Vision and Mentor Graphics sell tools which automatically generate vhdl/verilog wrapper logic for these modules given a specification.