CAD and VLSI

ya...global is with global routing estimates (dela...

2009-10-28T16:20:00.306-07:00

ya...global is with global routing estimates (delay model= elmore!)

Nice idea and it has worked for me quite a bit. ...

2009-10-28T16:17:42.406-07:00

Nice idea and it has worked for me quite a bit.

But unfortunately hold is a killer because there are a lot more hold failing paths in the 0-20 ps range than in the 80-100 ps range.

Less margin in global mode would mean (a lot less hold buffers in global mode) a lot more hold buffers in final mode.

"Global" means based on global routing estimation?...

2009-10-28T11:27:33.961-07:00

"Global" means based on global routing estimation?

How about fixing to Global but with less margin, so you're not flooding in the buffers. Then, post-route, put in the desired margin and fix fewer remaining violations.

John Busco

Hi Nick, Thanks for sharing this. ARM has been a ...

2009-10-28T06:25:14.973-07:00

Hi Nick,

Thanks for sharing this. ARM has been a solid innovator over the times and this should be another gem from their design powerhouse.I am new to your blog and I am sure I will see more interesting stuff in here.

renjith

Most industrial routers support eco routing. But I...

2008-06-01T06:46:00.000-07:00

Most industrial routers support eco routing. But I am not sure if that facility is there in the routers.

As long as ECO router does not cause any major perturbation to already routed nets (minimal detouring or rip-up/reorute of other nets), I guess it's okay.

Have you guys used ECO routing tools/feature ? I h...

2008-05-29T21:23:00.000-07:00

Have you guys used ECO routing tools/feature ? I have heard Cadence Nanoroute supports ECO routing...I want to know if it supports a feature using which u can minimize the number of metal layers affected ?

--Nil

The URL for the McClellan opinion piece is truncat...

2008-05-26T16:18:00.000-07:00

The URL for the McClellan opinion piece is truncated in your post (but still available in the source to the post) it's here

It's an thought provoking commentary.

The differentiation comes at Tech. Mapping support...

2008-05-09T13:03:00.000-07:00

The differentiation comes at Tech. Mapping support:
http://www.cadence.com/company/newsroom/press_releases/pr.aspx?xml=032508_eco

Hi Nil,It would be nice to hear what the different...

2008-05-09T03:49:00.000-07:00

Hi Nil,
It would be nice to hear what the differentiating features are with this particular cadence product compared to the rest of the products out there (synopsys and Magma both have OK ECO flows)

Yes, I interned in the same group in Cadence a sum...

2008-05-08T14:36:00.000-07:00

Yes, I interned in the same group in Cadence a summer back!

Have you guys heard about Cadence Conformal ECO? I...

2008-05-08T08:19:00.000-07:00

Have you guys heard about Cadence Conformal ECO? It's a new product they announced -- sounds like the old idea of Synopsys ECO Compiler. Maybe Cadence has done it better. :-)

Hi,ECO falls under that purview and happens to be ...

2008-05-08T01:49:00.000-07:00

Hi,
ECO falls under that purview and happens to be one of the problems I am looking at right now from research angle: as in what precisely do current tools/algorithms lack in tackling practical ECOs ? I would love to hear your view on it.

Another question is what do you mean by ECO ? a function change or timing requirements change or the design is giving you too much trouble with

Hi Nilesh,We have seen industrial level CAD tools ...

2008-05-06T19:45:00.000-07:00

Hi Nilesh,

We have seen industrial level CAD tools choke on eco's > 15-20K gates in size (choking could be related to timing/congestion/drc convergence of the overal design).

Most tools can handle capacity, but thats not the only issue here.

The ECO could be very design specific as it depends quite a bit on where the ECO cells got placed (for timing/congestion reasons)

Hi Nick,Specifically referring to "monstrous" ECOs...

2008-05-06T16:33:00.000-07:00

Hi Nick,

Specifically referring to "monstrous" ECOs, how big can they practically be in your case ? I mean when do you call a changed specification/design correction to be a "monstrous" ECO ?

--Nil

Hi John,It's a small team (5) of pretty smart indi...

2008-02-07T06:26:00.000-08:00

Hi John,
It's a small team (5) of pretty smart individuals at a big semiconductor company, but unfortunately not everyone in the team (except 1-2 of us) have the experience doing a tapeout of this magnitude and complexity within a 3-4 month schedule.

--Nik

I sympathize with all these points! Do you have to...

2008-01-31T13:16:00.000-08:00

I sympathize with all these points! Do you have to solve them all yourself?

I'm fortunate to work with a relatively big team to address such questions.
I feel extra sorry for guys at startups trying to tape out these nanometer chips on a shoestring budget.

Hey! Good post. I can't vouch for the ILP out-of...

2007-02-28T11:40:00.000-08:00

Hey! Good post.

I can't vouch for the ILP out-of-order reference, but your description of the various technologies at-hand was very good.

I have a website (blog) called DFT Digest, which concentrates solely on design-for-test issues and trade-offs, if you're interested. It's light on the math, heavy on the methodology.