High performance ARM cores and CAD Reference methodology

It is quite funny the kind of deliverables (reference methodology) a few CAD vendors (in the top four) provide to customers as a reference methodology (RM) for Implementing a high performance ARM core.

1. Sometimes the RM is incomplete
2. The vendor never managed to get even within 50-100 MHz of the performance quoted by ARM in their data sheet(including OCV and SI).
3. The vendor used unreasonable OCV and SI targets to get to the desired frequency.
4. The methodology has formal verification Issues
5. There is no mention of a Hold Margin during hold fix. In this day and age people sign off with a hold margin in PT with quite pessimistic OCV and SI settings.

I am referring to a quick TAT ASIC EDA flow using standard TSMC libraries to achieve frequencies quoted by ARM in the data sheets.

Extra effort and customization might be required to push it over and above the frequency quoted by ARM for an ASIC methodology, which is understandable and reasonable.

Otherwise it fails to satisy the objective of the core (it being an IP) and the amount of money and time which a company has to invest in trying to implement the IP.

Do tell us what your positive/negative experiences have been if u have worked on an ARM core and if a CAD methodology/vendor has really helped boost performance of your core in the past.

It is time that ARM started promoting 1-2 vendors over others if in fact they feel that TAT can be reduced as a result of changing the vendor in order to achieve the desired performance on the core.

Although this does not satisfy the criteria of an ideal IP, who cares as long as people get what they want!