Design of a 50M gate ASIC..

These are 10% of the problems ASIC designers face in Physical Design and STA of a 50M gate count ASIC.

Some of the problems are:
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1. Not many CAD tools exist out there which can handle this design flat atleast in an initial prototyping phase (synthesis + cluster placement) to arrive at the initial logical/physical hierarchies.

2. This leaves us with 50 partitions (assuming an ideal partition size to be 1 Million gates). 1 Million gates is an ideal block size which can be closed Netlist to GDS typically in < 1 day's time frame in current CAD tools. (timing closure + routing + clean LVS and DRC).

50 blocks is very very tough to manage though.

A better tradeoff.......

May be we can have 10 partitions ideally with 5M gates each. But my block run times will be higher and I have to live with those block run times (netlist to GDS might take 3-4 days or more easily).

3. K-way partitioners (k<5,6) work best if the partitions are 5-6. Not sure how good an initial seed partition is going to end up being if we have 50 of them. So I will freeze on a max 10- or worst case 20 partitions.

partitioning has traditionally been reducing pin counts as the main cost function. Any other cost function is EDA Sales innovation.

4. Reality check == Partitioning is not timing/congestion/power driven.

5. There cant be much glue logic at top level and it is a sliced floorplan. This is the simplest floorplan which is possible (minimal glue logic at top).

6. People have designed these chips routinely. But they were a bunch of very smart chip designer's sitting at IBM Microelectronics. (Not monkey's pushing CAD tools)

7. This is a 45nm chip? 200-250 mm2 die size. what is my yield gonna look like? How many times do I keep spinning this thing through the fab?

8. How am I going to reduce leakage on this chip? Power gating? Multi-Vt? V VFS? Some special-K dielectric which the fab is going to employ? All of the above?

9. The complexity is difficult to fathom if the chip has multiple modes of operation (2-3 modes is also very very hard). what if it has multiple power domains? (3).

10. How do I to generate the block level constraints? My netlist is getting generated in a bottom up fashion. Although I would love to push top level constraints down to each of the blocks, I will have a schedule slip of 6 months if I wait for my top level to finish :(

11. How do I plan my block budgeting?

12. The constraints will be quite tough to manage for all modes/corners. How do I clean up the messed up constraints? in each mode/multiple modes? across corners?
Do I use automatic constraint generators? validators? How correct are they going to be? How much time do I waste trying to see if these tools are production worthy?

13. Some of my sub chips have 200+ macro's. Are mixed placers (capable of simultaneous std cell + macro placement) going to help my woes atleast with a good initial seed placement?

14. How do I design my power plan? IR drop and EM limits, routing congestion, adequate de-cap insertion?

15. How the heck do I handle those monsterous ECO's? Reconfigurable filler cells (Metal only eco)?. what spare cell planning will help?

16. How do I do the final timing signoff? Incremental timer updates..how long are they gonna take in STA tools? Do I use ILM's? Across corners and across multiple modes? Tough to manage so many timing models.

Validating the ILM's for correctness is another big challenge.

17. How many clocks does this monster have? Clock tree (CTS) is a nightmare with multiple modes and across corners.

Also what if the clocks transcend across multiple blocks. I need to do proper clock planning early on to avoid the clock from jogging too much across multiple modules running at different voltage levels (and modes).

18. I hope my manager doesnt commit on a final netlist 2-3 week turn around time (netlist to GDS2) to the end customer.

Let me know your thoughts :)

on routing (Routing-2)..

Within the physical design flow of a multi million gate ASIC, one of the most critical and notoriously difficult steps to perform is Routing.

To tackle this problem, it has been split up into sub problems such as

1. Global routing
2. Track routing
3. Detail routing.

One of the most critical and initial steps is global routing. The quality of this routing solution has a direct impact on

1. chip frequency
2. Area
3. power consumption
4. cycles required to complete design cycle.

Global routing takes us to a stage where signal nets are coarsely routed under a given placement solution so that wire/via spaces are allocated to each signal net.

while the objectives at this stage are routing multi terminal nets (nets with > 2 terminals), taking net criticality/slack into account, accounting for congestion, even the most simple version of the problem (i.e routing a 2 terminal net under congestion constraints) is NP complete.

Given the advances happening in VLSI fabrication technology (<65 nm), the latest advances have posed a latest set of issues to be solved and have put further pressure on global routing technology (especially handling the Non default rules at global routing stage).