Gridded and gridless routers (Routing-0)

Interconnect optimization (routing) is crucial in minimizing delay, noise and optimizing reliability. Variable rules for deep submicron (width and spacing) make the job of a VLSI Router so much more difficult.

It's about how effectively we use the available space for routing with such complex design rules for < 65nm technology nodes.

Gridless routers are run time and memory intensive [when working on manufacturing grid (smallest geometry manufacturable by a fab!)]. Bringing down the run time/memory requirements is a challenge which the industry faces. This has resulted in the evolution of data structures like connection graphs and tile graphs.

Searching for paths on a uniform grid graph is so much more easier (Gridded router), but this wastes space available for routing with variable rules and new 45nm rules (litho + cmp rules!).

This is a huge topic for discussion. So Please feel free to leave behind your comments on what you think about this technology.

An interesting article on cell model creation for statistical timing analysis

Meeting timing at the worst or best-case corner can be very challenging, lengthening design schedules and negatively impacting power consumption. With a large range of potential delay values, often with a difference of as much as 50 percent or more between the slow and fast process corners, it becomes harder to meet both setup times at the worst-case corner and hold times at the best-case corner.

Read the remaining portion of the interesting article at..
http://www.eetimes.com/showArticle.jhtml?articleID=190100003

The great STA/Formal verification vs Gate level simulation debate

why the heck do we still do gate level simulations? Are they not run time/memory intensive? what is the confidence with which we can tapeout a chip without a gate level sim?

here are some views on this topic from different industry veterans at deep chip.

I didn't want to miss this interesting debate. Hence included it in the blog.

This post is from John Cooley's deepchip.com
http://www.deepchip.com/items/0421-01.html